The LTSpice is a great and free simulation tool for analog circuits. During design phase of my buck converter I needed to simulate the digital part, notably a fixed pulse length generator triggered by signal edge. The LTSpice is great for analog, but when it comes to digital domain, very few parts are in the standard library and very a very little support can be found online.
Let's start with the edge detector. This can be implemented in analog domain in few parts, but such solution slows down our simulation by calculating something we don't need. Fortunately this can be done in a simple and efficient manner in a digital domain.
The edge detection is based on a simple idea, when you take the signal and delay it a little bit, you can detect the edges simply by running the unmodified and delayed version through the XOR gate. In real world this is usually done by connecting several buffers in a row, in LTSpice you just need to set the td parameter to the buf component.
The rising edge detector takes a little more thinking, but the idea is similar, this time, invert and delay the inverted signal and run both signals through the AND gate.
And finally the falling edge detection - invert and delay the input signal and run it through the NOR gate.
All the three detectors implemented in the LTSpice can look like this:
The td value defines length of the generated output pulse, be very careful about this value. If it's lower than the input pulse length, the output pulse will be shorter than you expect! Also the transient simulation with way too long simulation step can miss a shorter pulses generated by your edge detector! And if you make the value longer than your pulse length, you'll even miss the edge completely!. Tune the td carefully for reasonable simulation step and expected input pulse lengths.
The only part in the LTSpice Digital library that could be usable for pulse generation is the Counter which requires a clock input and is quite horribly documented. I found a nice library that solves a part of the problem for me on the ltwiki. The library contains a Delay block, anything that goes inside will go outside in a specified delay time and the part definition is only few lines long and therefore quite fast to simulate.
The monostable pulse generator is very easy to make with the delay block, see the image below. The input pulse (generated e.g. by the edge detectors above) sets the SR Latch output to high, at the same time, the pulse enters the delay block and after defined period of time, this pulse restarts the Latch output to low. And as a result you've got the pulse of defined length (by delay time) created.
This generator is not perfect, just try to kick the circuit more often than once in a output pulse length, it will go nuts. But such simple solution works for my case, if you need something better and more robust, use that thing on your neck and have as much fan as I had during designing and testing the circuit.